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Issue:
A lot of targets that share the same HDL sources but have different pinouts, synthesis and implementation strategies etc.
Right now I repeat most of the filesets part for each target, like…
m-kru updated
5 years ago
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## Steps to reproduce the issue
Let Yosys run read_verilog on the wb_common verilog file from wb_common.
https://github.com/fusesoc/wb_common/blob/master/wb_common.v
## Expected behavior
The…
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For example:
fusesoc gen run [--export-files] my_core_name output_directory
This would create the output_directory, and run any generators that need to run placing the
final generation products …
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I'm considering updating the picorv32 core for the FuseSoC standard library, but it would be great to have a tagged release that I can use
olofk updated
5 years ago
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Im having an issue using the fusesoc pgm de0_nano command. I used `fusesoc build de0_nano --bootrom_file=~/.local/share/fusesoc/orpsoc-cores/systems/de0_nano/sw/spi_uimage_loader.vh --spi_flash_file=.…
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Im still struggling by figuring out how fusesoc generates the build-tree...
I´m interessted in using fosesoc Sim(ulation) with a simulator target other then Verilator but fusesoc stops thenafter wi…
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**Is your feature request related to a problem? Please describe.**
I am a developer of [gim](https://github.com/dominiksalvet/gim) project. It is a simple Git-based installation manager and it can in…
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Is it desirable to add libraries, that are not vendor libraries or popular libraries (like OSVVM or UVVM) to the vendors directory?
Namely, I work with the [IPbus](https://github.com/ipbus/ipbus-…
m-kru updated
5 years ago
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Following the 1.4.1 Building Hardware fails on the the newly added Parameters: CORE_ENABLE_FPU + CORE_ENABLE_PERFCOUNTERS
BASE_CONFIG is mismatching:
/opt/optimsoc/prebuilt/verilator-3.902/bin/ver…
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The current implementation of the system_2x2_cccc does not work on the VCU108. The reason is that the Xilinx IPs for the `xilinx_axi_register_slice` and the `xilinx_axi_interconnect_4to1` have been de…