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Would firmware update over CAN be desirable?
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### Part 1 - Population overview
- [x] Walking routes to the L (https://team.cartodb.com/u/stuartlynn/tables/l_walking_route_block/table)
- [x] Use walking routes to get block groups
- [x] Join demogr…
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Gated Bus pass-trough - basically a pass-trough for a whole bus something similar to a RedPower2 Bus Transceiver , possibly with a "translation method" to swap certain colors with other ones, and with…
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Latest versioned CI run failed with the following error message:
`[2022-10-17 16:24:16,059] {taskinstance.py:1150} ERROR - invalid input syntax for type numeric: "inf"
CONTEXT: COPY egon_etrago_li…
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```
What change would like to see?
Atmega 1280s, 2560s support multiple SPI buses and it would be very handy to be
able to use them.
Why?
I'm on the arducopter team and in the APM2 hardware we use o…
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When using the GenericStorage with an investment optimization approach like this:
```
electric_storage = cmp.GenericStorage(
label="electric_storage",
inputs={el_bus: solph…
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Integrations should be executable outside of resource closures in certain cases for the following use cases:
* Testing
* Using logic during synthesis
* [ ] Create `standalone` integration type
*…
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I have observed on my own test Digitransit instance that buses are shown both on the linear trip timetable and on the actual map as markers, where trains are not shown on the route map even when they …
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En https://github.com/mapanica/coordinacion/issues/3 tenemos un papel con algo parecido a un horario de los urbanos de Estelí: [Horario Estelí Urbanos.pdf](https://github.com/mapanica/coordinacion/fil…
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hi
i was which pin on fpga is being used to connect to the input of the clock tree if we wanted to use clock from fpga as ref clock. also can you please confirm the the voltage on the GPIO pins; f…