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Scala FIRRTL Compiler supported annotations to control the emission of randomization code at the top of the file, which can be quite noisy. In particular the `CustomDefaultRegisterEmission.disableRand…
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Consider:
```
circuit Top :
extmodule Foo :
input reset : Reset @[FizzBuzz.scala 123:10]
input in : UInt
output out : UInt
module Top:
input in : UInt
output out : U…
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### Description of Issue
```
NVIM v0.9.0
Build type: Release
LuaJIT 2.1.0-beta3
system vimrc file: "$VIM/sysinit.vim"
fall-back for $VIM: "/nix/store/h58i7gppfamlnadkwzj35wxc9sklpdsx-neo…
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Bug is present on both head of main and CIRCT sifive/1/20/0.
Consider:
```
circuit Top : %[[
{
"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
"keys": [
{
…
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There should be the same statistics printed for all simulators.
- Startup time(here Treadle is expected to score much higher)
- Simulation frequency
- Total time
```
test ThingAMaBob Succes…
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We have some test failures on Windows. In addition to all the LLHD sim tests (due to `llhd-sim` not being built #374), the following fail:
```
********************
Failed Tests (12):
CIRCT :: Di…
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This issue is subsequency of #4399
OS: Ubuntu 20.04
CIRCT: SiFive Internal Release 1.24.0
Chisel 3.5.5
**Description:**
The generated size of Verilog file has been reduced but it's function seem…
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when I try to parser **Accumulator** low Firrtl code through treadle, 2 syntax error(s) detected.
the low Firrtl code:
```
val accuFirrtl1: String =
s"""
|circuit fib :
…
wky17 updated
2 years ago
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```
/home/jodemme/circt/lib/Dialect/Comb/CombFolds.cpp:117:10: warning: 'ComplementMatcher' may not intend to support class template argument deduction [-Wctad-maybe-unsupported]
return Complement…
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On Ubuntu 22.04, clang 14.0.0, in debug mode, commit 23f4505a895418f355e3c49c2a444ccf3e4c8d71:
```
Slowest Tests:
--------------------------------------------------------------------------
15.16…