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PoR requires these are ordered by program order.
This might want to be loosened to simplify implementations.
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**What will you do?**
This project aims to explore the performance tradeoff for the number of logical vector registers and performance in executing vector based benchmark. This project is motivated…
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Binary is compiled by https://github.com/s117/riscv-gnu-toolchain/commit/d0bdaa9a282a32cc68e6203098dc1162021ceba7
```
$ spike -m8192 pk -c omnetpp_s_base.riscv-m64 -c General -r 0
Requesting ta…
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## Bug Title
USer ISA page 30 states that for RV32I, SLLI, SRLI, and SRAI generate an illegal instruction exception if imm[5] != 0
APP: formalISA
parameter PULP_XPULP = 0 …
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I was trying to build go-1.14.9 and go-1.14.10 on Gentoo, but tests failed. So I tried 1.15.3 and git master -- the same. See the failure below.
This is a x86 system.
### Does this issue reprodu…
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The binary is compiled by the Linux Toolchain https://github.com/s117/riscv-gnu-toolchain/commit/d0bdaa9a282a32cc68e6203098dc1162021ceba7
```
$ spike -m16384 pk -c nab_s_base.riscv-m64 3j1n 201403…
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There are some instructions that my processor does not support. How can I prevent gcc from using these instructions?
I designed a simple riscv processor, which has very few instructions, only a doz…
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via last night's linux-next: https://travis-ci.com/github/ClangBuiltLinux/continuous-integration/jobs/346493536
```
In file included from arch/riscv/kernel/asm-offsets.c:10:
In file included from .…
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I'm trying to build rust with profiler support in Gentoo Linux.
The `config.toml`:
```toml
[llvm]
optimize = true
release-debuginfo = false
assertions = false
ninja = true
targets = "X86;ARM…
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When connecting OpenOCD I get the following warning:
Info : datacount=2 progbufsize=0
Warn : We won't be able to execute fence instructions on this target. Memory may not always appear consistent.…