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The PRs from @xuminready has been merged which updates the source but no [new releases](https://github.com/parallella/parabuntu/releases) were published.
There is a [forum thread](http://parallella…
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Hi, @Dolu1990
I'm using litex with your naxriscv and trying to figure out how I can integrate my IP with your code. My ip uses axi4
and it has:
> (1) an AXI4 master and a slave port;
(2) the m…
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Hi all-- first, I actually have the TexElec hardware, but from what I understand, on the bus it should be the same.
It disables the joystick port (like the model 56) because of conflicts with SCSI …
mlyle updated
3 years ago
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How to repeat:
1. Run ```$ placement_tool=graywolf qflow gui```
2. Choose ```Technology=osu035```
3. Choose the Verilog file ```map9v3.v```
4. Hit ```Run``` for Preparation, then for Synthesis
…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X]…
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```python
class A(metaclass=abc.ABCMeta): pass
class B: pass
A.register(B)
a: A = B() # currently E: Incompatible types in assignment (expression has type "B", variable has type "A")
print(isins…
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(1)Is this function only available using the questasim tool?
(2)I run the following command.
```
cd ara
make -C apps bin/hello_world vcd_dump=1
make -C hardware simc app=hello_word vcd_dump=1
…
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@umarcor @LarsAsplund @JimLewis @eine @suzizecat @Paebbels @nfrancque I have been talking a bit with @qarlosalberto about potentially creating a sphinx builder/autodoc plugin for HDL, although I'm mor…
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Publishing this extension https://open-vsx.org/extension/AndrewNolte/vscode-system-verilog
https://github.com/AndrewNolte/vscode-system-verilog
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/cc @carlosedp @mithro @cmarqu @mgielda @PiotrZierhoffer @kgugala @qarlosalberto @smgl9 @Nic30 @pepijndevos @drom @cavearr @juanmard @olofk @gojimmypi @ghuntley @mickaelistria @trabucayre @Paebbels
…