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Hi,
I installed cocotb version `1.6.0` using pip under my conda environment (python=3.9) on Fedora Linux x64.
When I execute `cocotb-config` I get the following error:
`
Traceback (most recent…
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TEST:
```
module dut;
PS7 PS7 (
.EMIOGPIOO (emio_gpio_o),
.EMIOGPIOTN(emio_gpio_t),
.EMIOGPIOI (emio_gpio_i),
);
endmodule
```
(Notice comma in line ``.EMIOGPIOI (emio_gpio…
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Reported by @gsomlo: https://libera.irclog.whitequark.org/litex/2021-09-27#30904583
cc @kgugala, @michalsieron.
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cocotb == 1.5.0
operating system == Linux x64
simulator == QuestaSim 64 10.7f
Python == python3
RTL language == SystemVerilog
Hello,
Top-level of project contains AXI Interface (by Interface…
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This starts with a bug in my nMigen -- I perform a comparison between unsigned and signed values. If this means behavior is undefined, then we can just close this issue.
It seems that simulation …
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Executing `make check-smoke` after `make install-src` on CentOS 7.9.2009 fails with `called Tcl_FindHashEntry on deleted table` errors. The log is pasted below:
```
$ make check-smoke
make[1]: En…
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nMigen thinks ``-5 / 2 = 3`` , but verilator disagrees.
I suspect this is because ``-5 // 2`` evaluates to -3 in Python.
# Commands
```bash
$python3 div.py
quotient = -3
$verilator -Wno-lint…
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I just learned that nmigen handles reset automatically, so in a simple module, I pulled out my own reset logic and tried
to use the reset logic from the clock domain. That does not seem to be a prob…
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请问Betapoint的相关介绍除了去年risc-v中国峰会上的分享后续还有更新介绍吗？
主要想了解下怎么把functional warmup得到的状态导入到simulator模型里的，另外除了cache状态还有哪些关键状态需要导入？
谢谢。
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Hi, as I known, force-riscv can generate random-instruction more faster than riscv-dv because of its base on C++. Did you have a plan to used force-riscv to generate random-instruction in your dv env …