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Greetings !
Awesome project BTW!
I did a quick pilot in my company using PeakRDL with Synopsys VCS, replacing an existing register module with SystemRDL specification + PeakRDL output. Worked Nice…
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Hi, I'm working on the step 4: Compile the overlay project on Vivado 2022.2, ubuntu 20.04. And the kria-vitis-platforms branch is [xlnx_rel_v2022.1].
When it comes to the command `source -notrace .…
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### Example
```sv
module m (
input [1:0] i1,
i2,
output [3:0] o
);
assign o = i1 + i2;
endmodule
```
Compile using:
```sh
verilator --binary m.sv
```
### Current O…
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Verilator 5.025 devel rev v5.024-5-g1012c054e does not allow more than one block with the same name within a single conditional generate construct.
Until Verilator is updated to remove this limitat…
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On 11/03/2020 15:19, Aleksander Czechowski wrote:
This repo is for learning in games, which are sort of generalized RL environments.
You need to compile it first, but by following the instructions…
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Hi, nice project you got there!
I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool.
However, when running only the RTL in Xcelium t…
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Hi,
All my module instantiation in my old code got error: "Unknown module type" after the update.
Simulation and synthesis by vcs and vivado still work.
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Hello There!
I would to ask if you could possibly add support for SystemVerilog? I'm pretty new to this so I'm not really sure if it will work but I've attached a link to a suitable compiler:
http…
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This could be a fun bit of data for each language.
Inspired by https://github.com/o2sh/onefetch/issues/1308
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I'm reading the KMD and UMD source code , but dosen't find the entrance or call to SystemC model. So could anyone tell me what the role the SystemC model play?