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When unwrapping a `DataDeclaration` partition declaring a single variable with qualifier (`const`/`static`/`var`), verible formatter crashes during post-traversal adjustments.
Example:
```verilog
m…
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Not sure whether we want to fix this, but we usually write
```systemverilog
return {
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While we do also require parameters/localparams to explicitly define a storage type in OpenTitan, there is one exception: "old-school" string parameters like this one
```systemverilog
parameter ARCH…
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Input:
```systemverilog
always_comb begin end
genvar i;
generate
for (i = 0; i < 4; i++) begin end
endgenerate
```
bad output:
```systemverilog
always_comb begin
end genvar i;
genera…
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Look at this code:
```verilog
typedef struct packed {
struct packed {
logic q;
} classa;
} alert_handler_reg2hw_intr_state_reg_t;
```
https://github.com/lowRISC/op…
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```
$ pytest test_vivado.py
===================================================================================== test session starts ===============================================================…
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Our to-be-published style guide explicitly bans the use of the `defparam` construct.
This feature request aims to enforce just that.
**Assignment:**
Implement this check as a rule inside here:
h…
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before today's update, I can create a config file in userpatch dir, `config-my.conf`
and I can use `./compile.sh docker my` to use veribles in config-my.conf.
after update, I cant.
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For example, the following module can't be parsed by verilog_syntax.
```
module A(
input var i,
output var o
);
endmodule
```
```
$ verilog_syntax test.sv
test.sv:2:12: syntax…
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From your simple testcase:
```
interface _if;
wire p_pkg::foo_t w;
endinterface
```
verilog_lint does not support this and display an error:
```
syntax error, rejected "::" (go/verible#synta…