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## 🐛 Bug
After converting Mistral-Large-2407 and trying to load the model for chatting or serving, the following error is presented:
"(mlc-llm) USER@MBPM3MVLB ~ % mlc_llm serve /Users/USER/LLM/M…
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I notice the Ryzen AI are using XLNX_VART_FIRMWARE and .xclbin file. I expect it was using the same technology as Xilinx Versal AI Engine. Will AMD open the document and interface for users to develop…
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**For Vivado questions, please use [Vivado forum](
https://forums.xilinx.com/t5/Vivado-RTL-Development/ct-p/DESIGN)**
**For Vitis questions, please use [the Vitis forum](
https://forums.xilinx.co…
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我已经仔细检查了硬件连线,vitis软件的中断部分也仔细和我的板子的中断例程进行了对比,还是接收不到apdone的中断,摄像头已经有显示了,请问您有什么意见吗,accel_conv的ip还需要在vivado中进行什么设置吗,引脚定义之类的?
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我使用的是Vivado 2018.3版本,打开工程之后无法看到BD文件。提问之前翻看了一下以往的issue,说是采用2019.2往上的版本。请问有2018.3的解决办法吗?(在网上找了一些发现没什么效果,再装2019.2的版本比较耗时间)
![image](https://github.com/adamgallas/fpga_accelerator_yolov3tiny/assets/11397…
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**Environment**
- OS: Ubuntu 20.04.5 LTS
- Vitis version: 2021.1
- Platform: [xilinx_u280_xdma_201920_3]
- TAPA version: 0.0.20220807.1
I wanted to use floorplan option in my …
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Is there any comment on the support of the ZedBoard (or any Zynq-7000 based device) with the 1.2 version of Vitis-AI?
I've seen #158, which states that it is generally possibly with some integratio…
sl33k updated
6 months ago
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I am having a DPU compatibility problem. I am using a ZCU104 with the DPUCZDX8G_ISA0_B4096_MAX_BG2 target, I changed the arch.json file as in https://support.xilinx.com/s/article/DPU-fingerprint-ERROR…
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Primary need.
Use a selected taxonomy to populate a gbif api call to get occurrence data into the application
guidelines
- use rgbif over web native api calls when possible
- Focus on a core…
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …