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Hello.
I have a question about the usage of nanotube-generated HLS modules.
I'd like to know what I should connect to the input and output of the AXI-Stream chain.
### What you are trying to do.
…
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I want to define a model of asynchronous reset flip-flop with timings. Those elements are very common to almost all FPGA architectures. There are neither examples of such logic elements in the docum…
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I notice the Ryzen AI are using XLNX_VART_FIRMWARE and .xclbin file. I expect it was using the same technology as Xilinx Versal AI Engine. Will AMD open the document and interface for users to develop…
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When compiling on raspberry-5 with raspbian OS, I get the following errors.
```
ghc -Wtabs -fmax-pmcheck-models=800 -hidir /home/mycroft92/bsc/src/comp/../../build/comp -odir /home/mycroft92/bsc/src…
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- MUX就是选择器,比如(a, b, en), 如果en为1则返回b
- 加法主要依赖异或门,a^b, ab不同则为1,相同则为0
### 半加器
半加器(half adder)的功能是将两个一位二进制数相加。它具有两个输入和两个输出,两个输入分别为 A、B,代表着等待相加的两个数,输出为 Sum、Carry;Sum代表加的结果,Carry 代表进位逻辑;
半加器的真值表为:
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cisen updated
2 years ago
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## Description
This error occurred when I was using MXNET on ARM64。
“/usr/local/lib/python3.7/site-packages/mxnet/libmxnet.so”,but in the path,lib file(libmxnet.so) is existed.
I installed MXNE…
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Hi,
I am trying to run Corundum using Alveo U250. It seems that I can see two interfaces in my host after installing mqnic kernel module. But I do not know whether the HW works correctly
Here is…
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Would it be possible to change the bus width size of NastiIO fron 64 bits to 128bits? That would apply to nasti.r.bits.data and nasti.w.bits.data specifically. The purpose is being to perform read and…
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It feels like there is a lot of duplication between all the symbiflow (and some non-symbiflow repositories like the Fomu workshop) around getting a nice sphinx setup.
It would be good if there was …
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I managed to add dualflexpress.v to my branch of [the CPU86 project](https://github.com/ecm-pushbx/cpu86) (a free 8088 CPU implementation design), running on the MAX1000 board. I wrote a little glue l…