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Hi,
currently I am implementing a simple Cache module intended to be synthesized for a Xilinx Zynq-7000.
I would like to map the register representing the cache's memory to the block ram provided …
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`qualcommax` is a renamed `ipq807x` target with `ipq807x` now as a subtarget, and its only present in master but buildbots are trying to build it for 23.05 as well.
Builder: https://buildbot.stagin…
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The FMCOMMS User guide claims "All the Analog Devices Vivado HDL reference designs have inside a ‘donut hole’ to accommodate custom IPs."
My team wants to know if we would be okay just using Vitis …
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Hi Anup, I'm trying to run Xvisor on a Rocket risc v core synthesized on the Digilent nexys a7-100t board FPGA but the boot process is stuck right after openSBI boot sequence.
At first, I thought th…
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I was working on working on PKCS11 TA functionality with Xilinx Zynq MPSoC QEMU simulator (Cortex-A53 - 64 bit) and noticed some warnings that are because of some incompatibilities between 32 bit and …
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Hi,
I am working on a project with the Xilinx's LLVM frontend. At this point I was testing the generation of LLVM IR with HLS streams. It turns out the compilation with Xilinx's clang fails. The erro…
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**Describe the bug**
`fpga done` does not appear to show the correct state of the done bit
`reset_fpga k` does not reset f1 as expected.
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I added the Board definition to make.py:
```
# ZYNQZ2 support -------------------------------------------------------------------------------
class PYNQZ2(Board):
soc_kwargs = {"uart_name": "s…
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I am using the most recent commit of this repo's master branch - Xilinx Bootgen v2022.2
When I attempt to create an aeskey with bootgen, the process will "hang" seemingly forever. Example:
```
…
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The current version of YARP does not support Debian 8.1 (currently installed on all of our Zynq devices).
We need to upgrade.
Which version? Ubuntu?