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Timed out after 1000 usec
üI00000 test_rom.c:133] Version: earlgrey_silver_release_v5-8368-g62844d571, Build Date: 2022-11-02 10:54:46^M^M
I00001 test_rom.c:235] Test ROM complete, jumping to fla…
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### Hierarchy of regression failure
Chip Level
### Failure Description
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:223) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTest…
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**Describe the bug**
Project fails to build using `Sysbuild` with an out of tree board.
This issue was first posted #53780 and fixed with #56801. The issue appeared again at aff9683387ff3fc6a88cb1…
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### Hierarchy of regression failure
Chip Level
### Failure Description
## Failure Buckets
* `Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']` has 27 failures:
* Test chip_sw_exa…
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### Hierarchy of regression failure
Chip Level
### Failure Description
* `UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench iss…
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### Hierarchy of regression failure
Chip Level
### Failure Description
```
UVM_ERROR @ * us: (sw_test_status_if.sv:75) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has…
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Per the AES closeout discussion document, with further details at https://docs.google.com/document/d/1Uzq6qSqOFqk0fDv0J1eUvnpGMR1wsF-03WhZUgIDKdw/edit#
Need to run Jasper Gold to check assertions rel…
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After `opentitan` rebase, the dvsim of: `hw/top_earlgrey/dv/chip_sim_cfg.hjson` fails on syntax error.
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* Test chip_sw_example_flash has 1 failures.
* 0.chip_sw_example_flash.1\
…
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### Hierarchy of regression failure
Chip Level
### Failure Description
~~UVM_ERROR @ * us: (cip_base_vseq.sv:250) [chip_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * rea…
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### Hierarchy of regression failure
Chip Level
### Failure Description
Test `chip_csr_rw` has 1 failure in 20 runs.
4.chip_csr_rw.1639693527
Line 305, in log /container/opentitan-…