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Noticed this while adding statistics, here's a small test case `names-cse.fir`:
```firrtl
circuit Names:
module Names:
input i: UInt
input j: UInt
output o: UInt
wire w: UIn…
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Hi, I want to build an emulator, so I entered `rocket-chip/emulator` and `make`. But somewhat the `VTestHarness.mk` is lost, and `generated-src/freechips.rocketchip.system.DefaultConfig` is whole empt…
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When I tried to build the spec on Mac OS, I got the following error:
```
$ make
make: *** No rule to make target `build/img/firrtl-folded-module.eps', needed by `build/spec.pdf'. Stop.
```
Wit…
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In the below, (run through firtool), export verilog spills some of the `_RANDOM` slices to temporaries, but never actually outputs the temporaries.
```mlir
module {
hw.module private @regInitRand…
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Consider:
```mlir
firrtl.circuit "Foo" {
firrtl.hierpath @nla_a [@Foo::@bar, @Bar::@a]
firrtl.module @Bar() {
%a = firrtl.wire sym @a : !firrtl.bundle
}
firrtl.module @Foo() {
…
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The following FIRRTL program
```python
; seed: 32
circuit top_mod :
module top_mod :
input clock: Clock
input arst: AsyncReset
reg tmp107: UInt, clock with: (reset => (arst, UIn…
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Hi, I am playing with the examples from the wiki. The second one (SimpleUnitWithParam) introduces parameters. However it seems that since a commit in 2021 this is somehow broken or the API has changed…
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Chisel Enum Annotations (see: https://www.chisel-lang.org/api/latest/chisel3/experimental/EnumAnnotations$.html) are kind of buggy. SiFive will just remove these. We should add some special casing dur…
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When adding the `--exclude module-externalizer` argument to `test/circt-reduce/trivial.mlir`, `circt-reduce` crashes during execution of the rewrite method of `RootPortPruner`. That means, when callin…
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Add a check that FIRRTL's `regreset` errors if the type of the reset value doesn't match the type of reset. E.g., the following should fail because a vector register is being reset to a ground type. …