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Would like to support both a bsv and vhdl flow here. I have little experience with the internals here but with some work I think we can get this going.
We'd want to support both ICE40 and ECP5 devi…
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Hi,
I'm trying to write an accelerator in a system with 2 PAC cards. However, I'm not sure how to handle the sw part. I'm following the 03 linked list tutorial. From my understanding, I should instan…
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This is the log when I use the latest openFPGAloader, hope this can be fixed soon.
```
lee@ubuntu:/mnt/hgfs/share$ sudo openFPGALoader -b tangnano9k nanows2812.fs
Jtag frequency : requested 6.00MH…
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[OpenFPGALoader](https://github.com/trabucayre/openFPGALoader) is an universal FPGA programming tool which supports a variety of FPGA devices and programmers based on JTAG, DAP interface, ORBTrace, DF…
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https://keplerstr.github.io/2019/04/04/FPGA%E5%B0%8F%E8%AE%BE%E8%AE%A1%E4%B9%8B%E5%A4%9A%E5%8A%9F%E8%83%BD%E9%9F%B3%E4%B9%90%E6%92%AD%E6%94%BE%E5%99%A8/#more
基于FPGA实现的音乐播放器(蜂鸣器版)
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I am trying to use AWS VM to run Carla simulator, is the g4dn xlarge machine good enough to run the simulator smoothly?
g4dn xlarge spec :
vCPUs | 4
Memory (GiB) | 16.0
Memory per vCPU (GiB…
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Hi, While compiling the quantized model for alveo U200 I'm getting the following error message:
(vitis-ai-tensorflow) Vitis-AI /workspace > ARCH=/opt/vitis_ai/compiler/arch/DPUCADF8H/U200/arch.json
…
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We need a way to visualize an RTDP configuration. This should include visualizations of relevant telemetry from the individual components that updates as the platform runs the simulation/workflow. For…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Red Semi is trying to get Linux running on the Nexys Video build of the CVA soc, and th…
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Hi,
I have downloaded the HRNET model for zcu104/zcu102 boards from the Vitis-AI v3.0 model zoo. I want to execute the model on the FPGA board but the directory doesn't contain the executable files…