-
Initialising a blockRam in Clash gives the following output -
```
// blockRam begin …
-
---
Author Name: **HyungKi Jeong**
Original Redmine Message: 2684 from https://www.veripool.org
---
Some codes in the 'fstapi.c' for MinGW has an error.
So I fixed as shown below.
```
D:\Progra…
-
---
Author Name: **HyungKi Jeong**
Original Redmine Message: 2682 from https://www.veripool.org
---
My program is using the the both classes 'VerilatedVcdC'(for GTKWave interactive mode) and 'Ve…
-
---
Author Name: **HyungKi Jeong**
Original Redmine Message: 2670 from https://www.veripool.org
---
In MINGW64+MSYS2 system, there is no "alloca.h" header file.
And I have got an error with this…
-
---
Author Name: **HyungKi Jeong**
Original Redmine Message: 2669 from https://www.veripool.org
---
LXT2 file dump working is fine.:)
But I can't found the way for GTKWave simultaneously wave du…
-
I'm trying to generate witnesses with yosys-smtbmc and I'm not having much luck with $past() functions in cover statements.
Yosys-smtbmc reports these cover statements as unreachable, even though I…
-
This could be my configuration but:
gtkwave -- when started, almost always vanishes. You have to cause it to jump to another tile for it to work. In some cases, the window is visible but non respon…
-
Hello. I want to implement a circular buffer and process data based on several previous signals. So i have a buffer and wires to previous signals declared like that:
```
wire [63:0] prev_value1;
wi…
-
**Please note we will close your issue without comment if you delete, do not read or do not fill out the issue checklist below and provide ALL the requested information. If you repeatedly fail to use …
-
Is there any way get internal signals of module (e.g. reg in module) in .vcd file without making input or output port when I use **traceSignals()**?
In SystemC, for example, LogicPoet(http://www.lo…