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## Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/10869283616
## Patch information
Applied patches: 1 -> 1
A…
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make[1]: Entering directory `/fac/proj/xxx/imperas-riscv-tests/imperas-riscv-tests'
make -j8 --max-load=4 \
RISCV_TARGET=riscvOVPsim \
RISCV_DEVICE=rv32i \
RISCV_PREFIX=/project/usr-xxx-RHEL…
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I went through the source and found jemalloc has already included some code for riscv support but couldn't find any doc/description to build it for riscv target on a x86_64 Linux, so want to confirm t…
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Examine Target.log have fail result
Warn : [riscv.cpu] Failed to read memory via program buffer
Warn : [riscv.cpu] Failed to read memory (addr=0x0) negative acknowledgment, but no packet pending
E…
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I run it with the command `spike pk benchmarks/dhrystone.riscv`
```bash
$ spike pk benchmarks/dhrystone.riscv
bbl loader
couldn't open ELF program: benchmarks/dhrystone.riscv!
```
I checked …
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Reproducer (it is a RISC-V-only bug):
```cpp
/*
* This is a RANDOMLY GENERATED PROGRAM.
*
* Generator: csmith 2.4.0
* Git version: 0ec6f1b
* Options: --max-funcs 3 --max-block-depth 3 …
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I am not very clear about this one:
https://github.com/riscv-software-src/riscv-isa-sim?tab=readme-ov-file#build-steps
![image](https://github.com/riscv-software-src/riscv-isa-sim/assets/3375461…
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### Description
A project which has to target 2 platforms shows strange behaviour when switching configurations.
### Steps to Reproduce
1. Import to RISCV project a configuration from ARM pro…
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I am getting following error in "make run-emulator"
verilator --cc --exe --top-module Top +define+PRINTF_COND=1 --assert --output-split 20000 --x-assign unique -I/home/farhad/Downloads/riscv-sodor…
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Based on the comments in https://github.com/iains/gcc-darwin-arm64/issues/49#issuecomment-972599628, I did a first run to build `riscv-none-embed-gcc`.
For now I applied only the 8 patches I alread…