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> Hi - can you please add support for SystemVerilog files (and maybe VHDL files too)? this is the main language we use
- from [jonnyboynewton](https://github.com/jonnyboynewton)
- [original issue]…
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I know this can be disabled via settings.json with `"editor.bracketPairColorization.enabled": false,`, but I need to disable it via my color theme such that it is only disabled when my theme is active…
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Hello,
What I want to describe is not actually a bug, but a possible improvement of user experience.
Sometimes during debugging or refactoring user may use wrong pattern assignments for dynamic or a…
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The core development team for VUnit does not have easy access to Cadence Incisive and Xcelium licenses which prevents us from running our acceptance tests on those simulators. To get a higher confiden…
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I am attaching the list of sample errors list here
Generated CODE:
`
always_comb begin
automatic logic [4:0] next_c = field_storage.CSR_MAC_ADID[i0].csr_mac_adid.value;
automatic logic load…
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This is more of a feature suggestion than request. Given how flexible uncapper already is, adapting it in a few ways would be absolutely brilliant. And if anything already is a feature, I guess that w…
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This works with VCS on https://edaplayground.com/ but verilator errors out:
```
%Error-UNSUPPORTED: t/t_interface1_modport.v:35:28: Unsupported: Modport clocking
35 | modport tb (input clk…
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Hi!
I'm using clash 0.99.3.
I'm working on implementing a fifo buffer using the blockrams that can have a read port and a write port that have have different widths. The efficiency of the usage …
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I've noticed this a few times, but occasionally I get a big confusing error message like this:
```
Type error:
sail-riscv/model/riscv_vmem_pte.sail:87.8-96.36:
87 | pte_flags[V] == 0b0
…
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**Describe the bug**
Slang reports an error for multiple continuous assignments in the following SystemVerilog code, specifically when assigning to slices of unpacked arrays. However, similar SystemV…