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When I call AnythingLLM's API in Python, and I ask a question in Chinese, the return is garbled:
```python
def anythingllm_chat(ipv4, port, api_key, slug, prompt):
url = f'http://{ipv4}:{port…
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I want to use the hls::atan() function for a self-defined ap_fixed datatype (ap_fixed).
When using vitis hls directly I can run the synthesis, but if I use the ROS2 integration I get the following …
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Hi,
I am trying to build the design for Alveou280 but getting the following error.
`ERROR: [HLS 207-812] 'ap_utils.h' file not found (/home/sahmed/ACCL/kernels/cclo/hls/eth_intf/../../../../driver…
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## Issue template
- Hardware description: Pynq Z1 Board with Zynq 7000 SoC
- RTOS: preferably FreeRTOS
#### Steps to reproduce the issue
I want to use micro-ros on the Pynq-Z1 board. This boar…
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If a file path has a '$' character in it, the parser for vhdl_ls.toml interprets it as an environment variable when it should not. $ characters are valid in windows file path names, and used in networ…
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By having this: Sinewave -> output gateway -> spectrum analyzer
Hub setting: zynq7000-7020-400-2, FPGA period:1e9/125e6 Simulink period: 1/125e6
Output is visible in scope but not in spectrum analyz…
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**你好,vitis编译过程中有如下报错:**
![image](https://github.com/huanggeli/yolov3tiny-ZYNQ7000/assets/30284028/3038c51f-8d48-44df-b880-b19f8413bdc9)
**检查ff.h,被包含在硬件平台中:**
![image](https://github.com/huanggeli/y…
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I am going to try to add support for the m2-hsio-module.
Is there any known issue for this?
http://avnet.me/m2-hsio-module
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I am trying to build the Vitis AI 3.5 image for either GPU or CPU and tf2 by running the following command
```
./docker_build.sh -t cpu -f tf2 #For CPU
```
and it fails, as it can be seen in
![…
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## 🐛 Bug
Compile Gemma-2b for Android in q4f16_0. Load model successful, but chat get error: OpenCL Error Code=-54: CL_INVALID_WORK_GROUP_SIZE Stack trace: File "/home/chaoqin/mlcllm/3rdpaty/tvm/sc…