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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ 3771.762672 us: (sw_logger_if.sv:522) [sram_ctrl_execution_test_main_prog_sim_dv(sw/device/tests/sim_dv/sram_ctr…
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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ * us: (cip_base_scoreboard.sv:433) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On inter…
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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ 2364.078220 us: (sw_logger_if.sv:522) [aes_idle_test_prog_sim_dv(sw/device/tests/aes_idle_test.c:115)] CHECK-fail:…
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When building opentitan with FPGA, bitstream is successfully generated, but looking at Hierarchy, I found that xil_defaultlib.xxxxxx are instantiated under many header files, but they are not added to…
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### Hierarchy of regression failure
Chip Level
### Failure Description
`UVM_FATAL @ * us: (cip_base_vseq.sv:293) [chip_prim_tl_access_vseq] Timeout waiting tl_access : addr=*`
### Steps t…
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Likely due to the changes being worked on in CI currently.
When looking at past results linked from https://reports.opentitan.org/hw/top_earlgrey/dv/latest/results.html the older entries are showin…
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Hello, I'm running into what I think is an instalation and/or compatibility issue. The pipeline continues up to the generating the *_mergedRepeats stage but fails to geneate the GFF files with the me…
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### Hierarchy of regression failure
Chip Level
### Failure Description
Test chip_sw_all_escalation_resets has 2 failures.
17.chip_sw_all_escalation_resets.1083579376
Log /container/opentitan-publ…
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### Hierarchy of regression failure
Chip Level
### Failure Description
```
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
``…
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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ 4510.502520 us: (sw_logger_if.sv:521) [sram_ctrl_main_scrambled_access_test_prog_sim_dv(sw/device/tests/si…