-
Using the following test case OpenROAD reports no antenna violations, but magic reports some quite large ones. An example:
```
Cell: fanout1050
Antenna violation detected at plane metal3
Effecti…
-
When I try to increase the output load ability of my block, after passing the OpenRoad flow successfully, the DRC is not clean. What should I adjust?
Attach my detail_route_issue_file:
[detail_rou…
-
For some reason, the variable here errors out. Version: e34045bca1b14e405a366a6ab5464c48969c8971
Screenshot:
![image](https://user-images.githubusercontent.com/7474152/161305393-63d762c9-5cb0-4502…
-
Hello,
I am working as a Lecturer in engineering college here in India. My Institution's name is Muffakham Jah College of Engineering and Technology, Hyderabad, India. I did my Masters in VLSI sys…
-
### Discussed in https://github.com/The-OpenROAD-Project/OpenROAD/discussions/1871
Originally posted by **GuzTech** May 17, 2022
Hello everyone!
I'm in the process of bringing up a new plat…
-
I want to change memory modules in a design with OpenRAM macros such as sky130_sram_2kbyte_1rw1r_32x512_8.v
I first need adapt pins and R/W functionalities of OpenRAM to our memory access port of a…
-
These suggestions relate to a cleaner layout that is hierarchical and logically organized such that it reflects the order of activity a user is likely to perform, default modes, exceptions - in that o…
-
After running `make DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk` everything is fine, until the GDS merge phase.
This is the error:
```
Elapsed time: 0:16.26[h:]min:sec. CPU time: user 16.11 s…
-
Looks like the high voltage devices
sky130_fd_pr__pfet_g5v0d10v5
sky130_fd_pr__nfet_g5v0d10v5
are not extracted with the nowell rules.
-
### Description
@maliberty
This is MPW shuttle design. https://github.com/nguyendao-uom/eFPGA_v3_caravel
Seems the macro covered entire die area and Triton route unable to access those pins.…