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Hi Tim,
Do we have, or are we planning to have, CBO operation for cache lines within openocd?
When putting BP's in the memory on a system with multi-level cache we need to invalidate the cache lines…
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As some may be aware, there has been significant development and change on Microkit outside of the mainline version. This currently lives [here](https://github.com/Ivan-Velickovic/sel4cp).
This iss…
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There seems to be new interresting family of RISC-V CPUs with very similar specs to the Espressif ones. Will you consider supporting them eventualy?
https://www.cnx-software.com/2020/10/24/bl602-bl…
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can this support other arch e.g. ARM, RISC-V? it appears to be x86 only?
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This model currently assumes there are 32 X registers i.e. the "embedded" ISA variants with only 16 registers are not supported.
The CHERIoT fork of this repo includes [a bit of a hack](https://githu…
rmn30 updated
1 month ago
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I'm going to implementing the support for the [Svadu](https://github.com/riscv/riscv-svadu). RISC-V Sail already has the [-d|--enable-dirty-update] flags. I wanted to get an opinion on if we should re…
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EDIT (2021-11-25): I replaced the description entirely ([originally here](https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-978840052)).
# Discovery
I found this issue when testi…
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There is probably an issue with the ASID signal in the SV32's MMU for the CV32A6.
1) ASID's width is hard coded in [cva6_tlb_sv32.sv](https://github.com/openhwgroup/cva6/blob/master/core/mmu_sv32/cva…
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both synclounge.tv and app.synclounge.tv are doing this
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Run the RISC-V on your computer and a peripheral on the Fomu connected over the wishbone USB bridge.