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**Describe the bug**
slang output is not reproducible on every run.
**To Reproduce**
I can't reproduce this here, because the output is the result of an inhouse design with 1000+ files, but befor…
udif updated
2 months ago
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Move all variable declaration in funciton to the head in the function declaration in transpiled code.
This is because SystemVerilog allows variable declaration at the head only.
#140
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I would like to use `Enum` to implement the design.
Currently, I can write the statement like
```
if (s.opcode == Opcode.LUI_OPCODE.value) | (s.opcode == Opcode.AUIPC_OPCODE.value):
s.opco…
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We have started to do some work but we didn't have an issue for it so I'm creating one.
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When running the above-mentioned example, uvm_fatal is thrown. Looks like APB monitor does not register any items during simulation.
Commands to reproduce the issue:
```
cd test/examples/simple/r…
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The `parameter` and `localparam` keywords are relatively long keywords.
So I'd like to propose alternative words instead of these keywords.
* `param`
* replacement of `parameter` keyword
* `…
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**Describe the bug**
I was running the verible linting rules on my SystemVerilog code but I noticed a small bug while linting `parameter` variables.
I am running the linting with the following rules…
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Please add SystemC temporal assertions implementation described [here](https://github.com/intel/systemc-compiler/wiki/Immediate-and-temporal-assertions-in-SystemC).
These assertions are intendend t…
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I realize that Verilator for UVM is still under development, but I would like to try it. I can't find any documentation on how to do this.
Is there any? If not, how does one run a UVM/SystemVerilog…
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The repository currently responsible for providing syntax highlighting for gdscript files is broken, and doesn't seem to be maintained. I suggest switching to another repo that is updated more frequ…