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FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations wi…
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**Type of issue**: questions
**Detail information**
I want to load a data file into a SRAM of RocketChip.
I have tried the following:
1. I have generated a SRAM on cbus like t…
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**Type of issue**: bug report
**Impact**: no functional change | increase efficiency in produced verilog
**What is the current behavior?**
Vec[Bool].reduceTree produces suboptimal reductions.
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The InstanceOp printer relies on the port names retained in the ModuleOp. When a pass makes a change to the ports, such as happens in LowerTypes, the InstanceOp and ModuleOp can have a different numb…
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FIRRTL updated to 4.0.5 today so the 1.6-SNAPSHOT jar of Treadle is broken.
At this commit: https://github.com/chipsalliance/firrtl/commit/f31416a8b7122ab29b3243c5d35670030e244455
Chiseltest fail…
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[first.fir.txt](https://github.com/llvm/circt/files/8646849/first.fir.txt)
```
$ firtool --format=fir -o=first.sv --verbose-pass-executions --strip-debug-info --mlir-pass-statistics --merge-connecti…
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If a constant wire is marked don't touch and used as the reset initial value, then CIRCT will complain that this is a "non-constant async reset value" during `LowerToHW` because it relies on IMCP to p…
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We are currently missing strict connect support in CheckCombCycles pass. For instance, we can't detect a cycle for the following IR.
```mlir
firrtl.circuit "top_mod" {
firrtl.module @top_mod(out %…
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This issue is really low priority, just wanted to record it. Inlining a module instance should cause the names of all things to be prefixed with the instance's name. The issue in MFC is that memorie…
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When I set `HasDTLB` and `HasITLB` to `false` in [Settings.scala](https://github.com/OSCPU/NutShell/blob/cf7963435b824106690152507bb9312c159b8d5e/src/main/scala/top/Settings.scala#L48), the project co…