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Hi @sylefeb!
Are you aware of the `mingw-w64-*-eda` tool groups in upstream MSYS2 repositories? That one is available for all environments (MINGW32, MINGW64, CLANG32, CLANG64 and UCRT64). See the l…
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By having this: Sinewave -> output gateway -> spectrum analyzer
Hub setting: zynq7000-7020-400-2, FPGA period:1e9/125e6 Simulink period: 1/125e6
Output is visible in scope but not in spectrum analyz…
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Hi,
I am creating this issue to discuss questions related to testing the double trouble after its successful assembly at Sierra Circuits.
I am currently at testing stage 1 that is powering up th…
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Hello there,
I want to use my FPGA-based EDA tool (similar with Zebu from @Synopsys) to run a single-core SoC. It utilizes Xilinx Virtex Ultrascale _XCVU440_ FPGA boards.
My current step is to …
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I have set my timeout to 1.0, but the connect() function gets stuck indefinately if no FCS is hooked up.
If I enable output for the connect() routine, it stops after these lines
```
#Status:
Cycl…
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Hi,
I have trying to use this code/library to program a Lattice CPLD. But unfortunately, I'm not have success on that.
I also tried to program the Xilinx CoolRunner II, and I'm having the same pro…
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>USB connection
"A drawback of the Apple Virtualization framework is that there is no implementation for USB forwarding as of when I'm writing this. Therefore, these scripts set up the [Xilinx Virtua…
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## Observed Behavior
When I tried to use github release "pulpissimo-v6.1.1", by using the "fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg32…
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@rwarmstr got another question if you have time: I profiled the `wide_vadd` tutorial with some small
modification to add float instead of integers. I also used 4 concurrent kernels.
Environment: …
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### Motivation :
MIGraphX can support multiple backend targets. It fully supports GPU target currently. It can target the CPU backend with limited functionality and FPGA support is in the BETA mod…