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Hello,
i'm extremely happy to find this project - as i'm struggling especially with a working linux module for the Lattice ECP3 Versa board. I was able to build from sources the ethpipe FPGA configura…
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_From @mithro on March 21, 2013 19:44_
Should support USB 2.0 backwards compatible.
Support transfer of raw frames rather than MJPEG stream.
Take a look at https://github.com/mossmann/daisho/tree/…
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People have a problem with the battery and, for example, turning off the smartphone under heavy load (when, for example, the battery still has 40%).
And all because of the lack of the ice40.bin calib…
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FireSim lets us synthesize all asserts or no asserts. Sometimes we want only some asserts.
Create a "boom_assert" macro which lets us specify levels for asserts.
For software simulation, we want…
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Hey there,
I'm new to working with FPGAs. I want to transfer Data from the IO's to the PC via Ethernet for that purpose I needed an Ethernet-Core and a college just recommended me that one here. So f…
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I am attempting to build the torus kernel for the LINPACK benchmark, but the build errors out in the link stage due to an invalid port mapping. I'm not sure I understand why this issue is occuring, bu…
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vga_bar_top.vhd,
vga_sync.vhd
logi_edu_test.xise point both these files as in local directory,
both should be: ../hdl/
wishbone_7seg4x.vhd
found in fpga-logi-dev
https://github.com/fpga-logi-dev/l…
peepo updated
9 years ago
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I used the automated make script to generate a Vivado project for FPGA implementation of Vortex. It creates the project however gives error during synthesis:
> [Synth 8-2671] single value range is …
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https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/example/unbox.html#FPGA-Development-guide
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### Test point name
[chip_sw_alert_handler_irqs](https://github.com/lowRISC/opentitan/blob/3f65c2a534fc75ed43f3af438f01afc5232bfc2b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson#L112-L121…