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Hey, I want to build litex project with ethernet peripheral. I succesfully builded project and generated bit file. I'm trying to loading boot.json file but I got this error.
![image](https://github.…
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HI!
I suggest gzip on-the-fly decompression to upload bitstreams.
Especially it's good for spi-over-jtag bitstreams database
each one from 2MB becomes only 3.3KB with gzip -9
emard updated
2 years ago
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Hi,
I got a chance to know LiteX recently from my friend who gave me a QMTech_EP4CE15F23C8N board, and practice linux-on-litex-vexriscv on it.
My friend told me to connect my USB-UART serial por…
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Hi All. I'm execute follow command got many errors.
```sh
litex-boards/litex_boards$ ./targets/qmtech_ep4cex5.py --with-ethernet --with-daughterboard --build
[...]
Info (176467): Node "sdra…
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I'd just like to report success in programming a QMTECH Cyclone IV EP4CE15 starter kit board.
Although not listed in the board or FPGA lists, it just worked:
`./openFPGALoader -v -v -c usb-blast…
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Hi,
I would like to try Linux with DE2-115 board and had made a change like
```patch
diff --git a/make.py b/make.py
index 339e664..625bc6e 100755
--- a/make.py
+++ b/make.py
@@ -487,6 +487,24 @…
lapnd updated
2 years ago
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Clicking "Shift DR" causes an error with:
`Traceback (most recent call last):
File "/home/klingler/develop/jtagGUI/Panels/LeftPanel.py", line 154, in shiftDR
self.mainW.shiftDR(event)
Fi…