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The FullAsynchronousResetTransform no longer removes its annotation, which can lead to problems where the pass is no longer idempotent. It seems like some work has gone in to minimizing the amount of …
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ARTIFACTS (.v) files not being generated after running after invoking the command- "rtl -a /demo/arch/pynqz1.tarch -s true" the RTL Summary is generated but not the .v files
OS- Windows 10
Errors:…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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using firtool-1.75.0 from github releases
I expect firtool to be able to lower enum types [as specified in the ABI](https://github.com/chipsalliance/firrtl-spec/blob/e53da0ca1b55d002e3c2c640b8a170b…
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Currently SystemVerilog modules are the only artifacts being produced with Utopia HLS. Additional output formats should be considered:
* Unscheduled DFCIR
* Scheduled FIRRTL
* VHDL (?)
* Verilog…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
Consider these tests: https://github.com/dtzSiFive/chisel3/commit/d8a3f1213c32a9e69fd6e15eaf4c9030ce2235f…
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Given:
```fir
FIRRTL version 3.0.0
circuit Foo: %[[
{"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Foo>reset"}
]]
module Foo:
input p : UInt
input r :…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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We should add a place to document the "Rationale" for FIRRTL's design, perhaps in the spirit of MLIR's rationales: https://mlir.llvm.org/docs/Rationale/ .
This has been proposed and requested by a …
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This is a tracking issue for an effort to switch Calyx's testbenching.
## Background
Currently, all Calyx-compiled Verilog programs use the same [standalone testbench](https://github.com/calyxir/…