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### Discussed in https://github.com/konosubakonoakua/blog/discussions/7
Originally posted by **konosubakonoakua** March 12, 2024
# zynq
## Manual
- [Embedded-Design-Tutorials](https://xili…
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Hello,
I'm building a softcore based on Briey.
I've the AxiCrossbar without Sdram and on the APB3Bridge 1 Timer, 1 UartCtrl, 1 Gpio.
On the APB3 I would like to add a custom Ctrl to transfer in a…
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Then in case of an overdrive the buffer will fail, not the FPGA.
Similar thing should be done on Kasli and Kasli SoC as well IMO.
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Theres both the xilinx Zynq soc with it's integrated FPGA (usually referred to as "the" rio FPGA), and the Lattice MachXO2-640. Neither of these have easy qemu support but i found https://www.xilinx.c…
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Hi,
I would like to run a GUI with this SOC on FPGA. so I can check a breakpoint etc.
there is a prepared GUI that I can do with it things like this?
thanks
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Hello,
I am trying to follow along with the labs and I was under the impression that this GitHub repository will have all of the necessary supporting material for the labs. There seems to be no DE1…
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# FPGA Development with wujian100 SoC - Part Nine: Working on Bugs - shieldjy
FPGA Development with wujian100 SoC - Part Nine: Working on Bugs
[https://shieldjy.github.io/post/FPGA-Development-with-…
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Hi everyone!
I am using an xcku035 FPGA, which is not listed in the following link:
https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2024.1/Xilinx_Official_Platforms
Is this going …
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hi
Why is there no script for compiling the Zybo bitstream in Vivado? I'm aware that it's possible to dynamically configure the FPGA's bin file (https://github.com/ikwzm/FPGA-SoC-Linux-Example-1-ZYBO…
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Hi, when I ran the flow I got the error message in both case.
I have checked the software requirements and version, then I used "$make check" to ensure that I don't miss any requirements.
Here are …