-
Having trouble reading 'CacheMisses' and 'InstructionsRetired' whenever I run the [dotnet/performance](https://github.com/dotnet/performance) benchmark suite. If I run the command from within the `src…
-
when I excute `/usr/sbin/pcm-latency --help`, it aborted with core dumped, Is this exit considered normal? the version of pcm is 202405
```/usr/sbin/pcm-latency --help
Detected a hypervisor/virtuali…
-
In the scenario where hardware performance monitoring (HPM) counters are shared between hypervisor and guest VM.
1. Configure `hcounteren` to assign a subset of HPM counters to a guest virtual mach…
-
I read the documentation about hardware counters and found that there is no introduction on how to monitor the active status of the matrix core. Is there currently a way to achieve this?
-
Hi, Is there any update plan for esp32S3 or esp32C3? These two chips are relatively excellent in the development of robots and smart devices, but the current micro ros does not seem to support them.
-
Hi,
Here is were i'm reporting the FMax mesurments and progress.
For VexiiRiscv (set as toplevel, after some tunning) with :
- RV32IMACSU + 4\*4KB I$ + 4\*4KB D$ + D$ hardware prefetcher + st…
-
Iai is very exciting! I love the idea of benchmarks that are *fast* and *deterministic*. But relying on Cachegrind has some drawbacks:
* Limited OS support
* Requires the user to install valgrind
…
-
Since there isn't an issue already open, would be possible to list which would be the requirements to have rr working on risc-v?
-
Seems that OpenSBI is emulating missing CSRs on illegal instruction traps, for example unprivileged `time` counter via access to `aclint-mtimer` device.
This is not always correct since the S-mode ma…
-
- link: https://developer.arm.com/tools-and-software/embedded/arm-development-studio/components/streamline-performance-analyzer
- intro: https://developer.arm.com/documentation/101816/0705/Getting-st…