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enjoy-digital
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litex_agilex5_test
Initial Test/Support of LiteX on Intel Agilex5 FPGAs.
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Missing modules l2_cache and altera_std_synchronizer_nocut
#16
sm3vhf
opened
1 month ago
2
Add board information in readme file
#15
sm3vhf
opened
1 month ago
0
Add LiteX PLL wrapper around PLL macro.
#14
enjoy-digital
opened
2 months ago
1
LPDDR4 AXI interfaces: decoupling clock domains
#13
trabucayre
closed
2 months ago
1
Improve AXI to LPDDR4 Access Efficiency.
#12
enjoy-digital
closed
2 months ago
5
FMax measurements
#11
Dolu1990
opened
3 months ago
6
Tunning frequency
#10
Dolu1990
closed
2 months ago
4
Bitstreams/Linux images.
#9
enjoy-digital
closed
2 months ago
12
Ethernet status
#8
trabucayre
opened
4 months ago
9
SDCARD access Status
#7
trabucayre
closed
3 months ago
2
LPDDR4 status
#6
trabucayre
closed
2 months ago
18
Bringup
#5
trabucayre
closed
2 months ago
7
Hardcoded paths
#4
Dolu1990
closed
4 months ago
3
LPDDR4 Qsys/Example
#3
trabucayre
closed
2 months ago
2
Resources Usage
#2
trabucayre
opened
4 months ago
19
Doc links
#1
trabucayre
opened
4 months ago
0