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After waiting a few days without a response from Lattice for a free license, I decided to move forward without Icecube2 (Linux is more convenient for me, anyway!)
I've installed icestorm and the re…
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Relates to: https://github.com/pq-code-package/tsc/issues/75
@ryjones asks if we could use small Graviton instances for benchmarking or whether there is the need for larger ones.
Let's collect s…
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Hey, despite Symbiflow mentioning ice40 support based on icestorm being supported, there seems to be no mention of it in this repo.
Is this anywhere on the radar?
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Hi!
I'm still playing with getting vtr working with iCE40 like architectures. The iCE40 has the idea that you have span4 and span12 lines which are not directly connected to the logic slices, I've …
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I have an Adafruit FT232H board I wish to use for programming SPI flash memory for the iCE40HX4K. This is one example of many generic FTDI boards out there. My intent is to program the flash memory in…
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HOMEBREW_VERSION: 4.3.7-36-ga40f327
ORIGIN: https://github.com/Homebrew/brew
HEAD: a40f32776f5d4020df4d11bb6acef9e845b70fb1
Last commit: 4 hours ago
Core tap JSON: 28 Jun 12:03 UTC
Core cask tap …
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# Version:
nextpnr-ice40 -- Next Generation Place and Route (git sha1 2898d81)
# Input:
```verilog
// look in pins.pcf for all the pin names on the TinyFPGA BX board
module top (
i…
BigET updated
4 years ago
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Getting the following error when running `make`:
```
ERROR: Unable to find legal placement for all cells, design is probably at utilisation limit.
```
It does, indeed, appear that some compone…
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VPR is does timing driven packing and routing. Hence it needs to know the timing information.
The iCE40 timing information is already known thanks to project icestorm. We just need to import it int…
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Hi, I made a slightly modified version of the board without much changing(downloading circuit unchanged), and now I have some problems with SRAM programming: moving R9 to R19 doesn't work. I'm using a…