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I am opening this issue to investigate allowing fusesoc to integrate migen or nmigen packages. I think this is a desirable functionality by several people.
Preliminarily, are there any high-level i…
FFY00 updated
3 years ago
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Hi, I wonder what is the clock frequency you used during the sampling process.
Regards.
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Hi,
I'm getting started on FPGAs (apologies in advance for noob behavior).
I've bought a Sipeed Tang Primer 20k ( https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html ) and I…
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Hello,
I'm trying to import verilog code into migen design as below:
First I created shifter.v:
```verilog
module shifter(
input sck_i,
input sdi_i,
output sdo_o,
input csn_i,
);…
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```
~/Build/Source/urukul ((v1.3.1) $%)$ python urukul_sim.py
Traceback (most recent call last):
File "urukul_sim.py", line 130, in
main()
File "urukul_sim.py", line 126, in main
sp…
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This isn't necessarily a bug, but I do feel it makes Verilog identifiers that Migen generates more difficult to read.
Migen has a tendency to decorate Verilog identifiers with the `__main__` prefix i…
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This issue concerns the [Migen/LiteX](https://github.com/im-tomu/fomu-workshop/blob/master/docs/migen.rst) page of thu tutorial.
It was not clear where I had to copy paste the extra Python code for…
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# Brief explanation
Migen / LiteX doesn't quite follow pep8 / pylint for good reasons. Extend pep8 and/or pylint to understand when it should allow violations. Extra additional checks for good Mige…
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The AXI streams exposed by the on Ultrascale (+) PHYs are not standardized TLPs. To support the Ultrascale (+) PHYs in LitePCIe (that operates on standardized TLPs), the AXI streams have been adapted …