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It looks to me like kratos and MyHDL languages are pretty similar in both approach and implementation. It would be wonderful if there was some collaboration to try and work out what commonalities can …
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OS: Windows 10
MyHDL version: 0.11.42 (stable Master branch)
Python version: 3.11.3
Description: I just updated my version of myhdl using `pip install git+https://github.com/myhdl/myhdl.git@maste…
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Can this project be compiled with VCS ？what is $from_myhdl and $to_myhdl?
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Can you please provide support for new myhdl block api.
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After the latest commit to `ip_eth_tx_64.v` (`9b5a8cf24aeeeee9d0eadabb3136f7e7722544e2`), the MyHDL testbench hangs indefinitely:
 path, and as a fun experiment I decided to build on linu…
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Since python 3.10, there is now support for case statements that more align with case statements in both VHDL and Verilog.
Raising this issue to track, potential, implementation in MyHDL.
[Pytho…
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Hi sir, I notice that the testbench requires cocotb, cocotbext-axi, and Icarus. I would be appriciated to if you could provide the verilog based testbench without using myhdl.
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@mkatsimpris in the interfaces (and some of the blocks) you define various
"assignment" functions/methods. In all of these cases these can
be replaced with a single block (DRY - don't repeat yoursel…
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### Environment:
Icarus Verilog : 10.1(stable)
MyHDL : 0.10
Make: i686-pc-mingw32 (mingw32-make)
OS: windows7-64bit
### First Try:
Just type 'make' as "README" said.
Cause errors as bellow:
…