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I tried using sqlelf to analyze a RISC-V ELF binary but got this error:
```sh
Unknown machine type for
```
I then realized that [x86_64 is the only architecure supported](https://github.com/f…
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This is a request that extends https://github.com/bpfman/bpfman/issues/1063.
I would like RISC-V support for `bpfman`, and in particular I'm currently using [Fedora on RISC-V](https://dl.fedoraproj…
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Hello!
After using the synthesis tool for generating the C code for the RISC-V processor, there are make build errors while further flashing the code on the MAX78000EVKIT board using VS Code.
``…
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![image](https://github.com/sevaa/dwex/assets/67872121/cf34da5b-b7e8-427d-b267-d0e20716ac24)
RISC-V does not have a t9 register, so I have looked into the dwarf result from objdump, and saw this …
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I'm building version 17.0.6
build options
cmake -S llvm -B build -G Ninja \
-DCMAKE_C_COMPILER=gcc \
-DCMAKE_CXX_COMPILER=g++ \
-DCMAKE_BUILD_TYPE="Release" \
-DLLVM_ENABLE_PROJECTS="clan…
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Just discovered OpenD today. It looks like there’s no ARM architecture support. Given that OpenD just began six months ago I understand there’s a lot to do and prioritize. That said, ARM is poised to …
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Hi,
It looks like the directory for 'risc_cpu' is missing. I'm just curious because all LLMs failed on this task.
Thanks!
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With the rise of popularity for RISC-V processors, and now especially with [Scaleway now offering RISC-V instances](https://labs.scaleway.com/en/em-rv1/), it seems that support for RISC-V …
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I noticed this when dealing with this:
- https://github.com/riscv-collab/riscv-openocd/issues/1098
The Spike targets for debugging use different ISAs/architecture specifications:
- https://gi…
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### What is the problem this feature would solve?
Be able to run bun on RISC-V Linux capable boards
### What is the feature you are proposing to solve the problem?
A build for RISC-V
### What alte…