-
I think we should switch from Make to CMake. This would have a number of benefits:
1. We can easily make the arch part of the targets instead of a Make parameter. I.e. instead of
```
ARCH=RV32 …
-
the make process is finished, and make run-emulator error shown as follow：
```
hessen@ParaComp:~/risc-v/riscv-sodor$ make run-emulator
running basedir/Makefile: make run-emulator
make -C emula…
hz0ne updated
8 months ago
-
RISCV_DEBUG is never used, but could be used to determine if the emulator should be built with certain single-instruction-level debugging support. Something to think about. The emulator is considered …
-
First trial of refactoring, the [wasm branch](https://github.com/ChinYikMing/rv32emu/tree/wasm)'s latest commit is the result.
Since `state_t` is a user-provided data, so all runtime defined value…
-
I'm running test cases randomly generated by Google's [riscv-dv](https://github.com/google/riscv-dv) on the sail-riscv c_emulator model.
It runs a few thousand instructions and then dies:
```
[23…
-
I am getting following error in "make run-emulator"
verilator --cc --exe --top-module Top +define+PRINTF_COND=1 --assert --output-split 20000 --x-assign unique -I/home/farhad/Downloads/riscv-sodor…
-
When attempting to compile the current version of this PR: https://github.com/riscv/sail-riscv/pull/197 I get an error when compiling the C file generated by Sail:
```
make csim
gcc -g -I /mnt/rus…
-
Hy there,
I completed the git clone and RISC-V front-end install to /usr/local/
After
```
./configure --with-riscv=/usr/local
make
```
I get
```
g++ -I. -MMD -I/usr/local/share/verilat…
-
需求：
1. 在 [LLVM24.09_mugen失败测试用例清单](https://docs.qq.com/sheet/DSnFpcEJyVnJYRGJ1?tab=BB08J2) 中找到测试套 tpm-tools 失败的测试用例
2. 在 [openEuler LLVM 平行宇宙 24.09 版本](https://repo.tarsier-infra.isrc.ac.cn/openEu…
-
When I run make reports after 'make run-emulator' I get errors like these grep CPI emulator/rv32_1stage/output/_.out
make: [rv32_1stage-report-cpi] Error 1 (ignored)
and test-results.xml is all 0
$ ma…