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The CI version builds OCaml emulator with a lot of warnings. The most severe of them is
````
File "riscv.ml", line 12439, characters 4-48:
12439 | Softfloat.f64_round_to_int (zrm, zv, zexact);…
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the make process is finished, and make run-emulator error shown as follow:
```
hessen@ParaComp:~/risc-v/riscv-sodor$ make run-emulator
running basedir/Makefile: make run-emulator
make -C emula…
hz0ne updated
3 months ago
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Hey, thanks for putting this up! I just tried running it, but it seems to be getting stuck on an unhandled exception:
```
❯ just run-riscv64
...
riscv_cpu_do_interrupt: hart:0, async:0, cause:0000…
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I'm running test cases randomly generated by Google's [riscv-dv](https://github.com/google/riscv-dv) on the sail-riscv c_emulator model.
It runs a few thousand instructions and then dies:
```
[23…
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`libfdt.so.1` is missing by default.
```bash
mx @ Phony in ~ |17:26:00 …
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I am getting following error in "make run-emulator"
verilator --cc --exe --top-module Top +define+PRINTF_COND=1 --assert --output-split 20000 --x-assign unique -I/home/farhad/Downloads/riscv-sodor…
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### Technical Group
Applications & Tools HC
### ratification-pkg
Technical Debt
### Technical Liaison
Bill McSpadden
### Task Category
Sail
### Task Sub Category
- [ ] gcc
…
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First trial of refactoring, the [wasm branch](https://github.com/ChinYikMing/rv32emu/tree/wasm)'s latest commit is the result.
Since `state_t` is a user-provided data, so all runtime defined value…
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When attempting to compile the current version of this PR: https://github.com/riscv/sail-riscv/pull/197 I get an error when compiling the C file generated by Sail:
```
make csim
gcc -g -I /mnt/rus…
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I followed this link https://github.com/kvm-riscv/howto/wiki/KVM-RISCV64-on-QEMU to start a emulated riscv host, but it failed with "sbi_hsm_hart_start_finish: ERR: The hart is in invalid state [21477…