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**Describe the bug**
The testbench step in SOF CI sometimes fails with pull requests not related to test.
**To Reproduce**
The CI launches scripts/host-testbench.sh test.
**Reproduction Rate**…
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Hello, I am attempting to write a testbench in verilog for the Arty A7 in order to send a simple message from the board to a mobile device, but am having trouble translating how the ethernet frame var…
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@nathanielnrn said that we don't have a way to drop in a harness and directly interface with calyx components to test them (please correct me if I'm misinterpreting this!). It seems quite useful to ex…
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How can use Verilog/system-Verilog testbench to verify the function of USB device?
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### What do I want
Working quarkus support for pro features like UiUnitTest
### Explain your problem
Two things, based on who reads this
**Testbench-Devs:**
There are multiple problems we…
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can you provide the testbench for this ?
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Hi
Is there any way to perform post implementation simulation on Vivado using SpinalHDL as simuation source? Or I have to write a new testbench?
Best
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The current setup is designed to work with CocoTB testbenches. Hopefully, we can get SV test benches to work. This will likely require some rework of the caravel-sim-infrastructure.
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there are binaries such as nnvm_testbench but no sources for them. Where can I find them?
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Your requirements could not be resolved to an installable set of packages.
Problem 1
- Root composer.json requires code-lts/doctum ^5.5 -> satisfiable by code-lts/doctum[v5.5.0, ..., 5…