-
It would be good to make Verilog testing independent from commercial tools - Synopsys VCS. A potential solution would be to use verilator instead.
-
Hello,
I have a very basic test bench with a vhdl top and two sub-modules: one vhdl and one verilog.
When trying to access the verilog submodule from a cocotb TB I have an error:
Unable to cr…
-
I want to run the simulation tests for this design , however I am unable to run the test with the command "make WAVES=1". I get below error.
FST warning: ignoring signals in previously scanned scop…
-
Environments
```
operating system WSL Ubuntu 20.04
cocotb version 1.8.1 (installed from pip)
verilator version 5.023 devel rev v5.020-176-g953249aa4 (built from source)
python version 3.10.14…
-
Hi Taichi,
I was searching for open-source AXI BFMs and landed onto your repository on github. This and your rggen is awesome piece of work and is very helpful. A big thank you to you for putting y…
-
To make sure to not accidentally introduce memory leaks or invalid memory access issues, we should run the tests with AddressSanitizer in the CI (maybe as separate after successful 'regular' testing, …
-
### Is there an existing issue for this?
- [X] I have searched the existing issues
### Describe the bug
Input `pre` is not used in the Verilog code for `DflipFlop`.
```verilog
module Dfli…
-
Hi, just wondering if the mixedsvvh flag could potentially be removed from this line: https://github.com/themperek/cocotb-test/blob/4924adc78712434dcd076060777239c04a22bfe8/cocotb_test/simulator.py#L5…
-
### Problem description:
I usually create my testbenches so that the signal generation section uses some idiom for "wait for the next clock rising edge" rather than waiting a fixed amount of time. T…
-
Hi @MarcoIeni,
I was running VUnit using this repository as a base, combined with github actions and simple but different source code.
The simulated verification fails to compile with the code …