-
When using the VHDL standalone formatter, "else" and "elsif" statements are indented one step too far to the right:
![image](https://user-images.githubusercontent.com/49446589/210272965-da43fdad-e72b…
-
It would be nice to give our HDL coding examples a uniform style. Ideally, we can find two style guides which are similar between VHDL and Verilog.
For Verilog I'd go with https://github.com/lowRIS…
-
when running emacs on windows without wsl, the formattter seems to do nothing.
Output in the VHDLbyHGB.emacs-vhdl-format:
> Debugger entered--Lisp error: (end-of-file)
> command-line-1(("--eva…
-
Just to get a final word on the format standards of the examples.
/cc @umarcor
- All files end with an empty line.
- No trailing white spaces at the end of lines.
- Tabs (not spaces) size 4. …
-
I have my first look on the clash compiler and about the readibility of the vhdl i'm raising some issues. I would like to know whether these issue are:
1. a shared concern for other developers
2. whet…
-
**What is your question?**
DISCLAIMER: This is a question and suggestion. let me know if you want me to seperate the suggestion into a seperate issue for tracking my feature request.
I actively us…
-
Formatter using VSG does not enforce prefix and suffix rules :
**To Reproduce**
rule file contains :
```
rule:
constant_015:
disable: false
prefixes: ['CST_']
```
vhdl fil…
-
## Intro
I'm investigating how hard it would be to add automating as a feature, as part of https://github.com/VHDL-LS/rust_hdl/issues/156. This project already has a parser, now we "only" need to a…
-
If the idea is to create an enhanced version of docco, why not get rid of pygments in favor of something that does not need to be installed, such as prismjs.com
This way users would need one less ste…
-
/cc @carlosedp @mithro @cmarqu @mgielda @PiotrZierhoffer @kgugala @qarlosalberto @smgl9 @Nic30 @pepijndevos @drom @cavearr @juanmard @olofk @gojimmypi @ghuntley @mickaelistria @trabucayre @Paebbels
…