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Hi,
I have a problem with entity name clashing with port name. My code is compiling with Modelsim but not GHDL. Here is the component interface:
```
entity ami_write is
port(
clk …
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**Description**
Not able to compile PSL verification unit file and bind to module.
**How to reproduce?**
I was trying to compile `dff.vhd` and `dff_psl.vhd` file using VHDL-2008 and VHDL-93 mode…
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Currently GHDL only supports identifiers (e.g. port names) up to 1023 characters long and (cleanly) terminates with a message like `test_long_log_msg/test.vhd:13:10: identifier is too long (> 1023)` o…
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**Description**
Creating a constant of a type that has unconstrained array of an unconstrained array causes stack dump.
**Expected behaviour**
Boundaries can be inferred from the default assignme…
suoto updated
3 years ago
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I'm aware that VHDL08 support is not complete. Just close the issue if it's a duplicate or not relevant, however I found it interesting, that the behavior differs between a code in package and entitie…
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**Description**
Unconstrained arrays of std_(u)logic_vectors are spec'ed in VHDL 2008. An implementation of it causes a bug print out.
**How to reproduce?**
```
library ieee;
use ieee.std_logic…
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And here the last two examples from ISE with problems, which are synthesized by `ghdl --synth` but fail with the plugin (same error,): [spmems.zip](https://github.com/ghdl/ghdl-yosys-plugin/files/4516…
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When using ghdl -c we might need to be able to put the various files
into different libraries.
For example, in microwatt, I need some in unisim (I have models mimmic'ing some xilinx stuff), some …
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Take the following series of commands:
```
ghdl -i --work=work --std=02 --workdir=work/ axi4_acp_writer.vhd axi4_acp_reader.vhd tb_axi4_acp.vhd axi4_acp.vhd
ghdl -m --work=work --std=02 --workdir=w…
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**Description**
PSL assertions without always are active at each cycle.
Instead they are active at each cycle:
```
sby --yosys "yosys -m ghdl" -f -d work/psl_always psl_always.sby prove
SBY 2…