-
When I try to open the post place & route implementation in fpga_editor from the tools menu, I get this error:
`/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/_fpga_editor: error while loading shared librar…
-
A few changes are needed for successful synthesis by the legacy Xilinx ISE toolchain:
- xst incorrectly implements the register file with ENABLE_REGS_DUALPORT = 1, but ENABLE_REGS_DUALPORT = 0 work…
-
I am getting the following error from the Xilinx ISE consuming CLaSH-generated VHDL:
> Line 6134: Signal `inst_chip8/clash_explicit_mealy_mealy_cpuout/_` is defined more than once.
I don't have …
-
Xilinx ISE is currently expected to be found in it's default install path of `/op/Xilinx/14.7/ISE_DS`. If ISE is not found in this location, the error message should be more informative and explain ho…
-
Hi,
I am one of the early purchasers for your Mercury 1 board and have contacted you a couple of years back regarding Linux support for Mercury board. I am glad that there is Linux support now for yo…
-
Hi all,
I am new to NetFPGA. I have a license for Xilinx ISE Design Suite 14.3, But it is used Xilinx ISE Design Suite 14.6 to work with NetFPGA-1G-CML. How can I use this version of ISE to work with …
-
When I try to build for example litex_boards/targets/linsn_rv901t.py with --with-ethernet, but add ntxslots=1 to the add_ethernet line, build fails with:
> Traceback (most recent call last):
> F…
-
What is required to be able to use Yosys with ISE for Spartan-6 and Spartan-3 devices?
I assume the following things are needed;
1) [ ] Description of the black boxes like SERDES and such,
2) […
-
Setting up the Xiling Spartan-6 involves installing a VM which is capable of running ISE 14.7.
From here we can write the firmware in VHDL if we connect the JTAG to the FPGA.
The development ar…
-
I am attempting to flash a bitstream to a custom FPGA board, called the [Dragon-L](https://www.knjn.com/FPGA-Dragon-L.html). It has a `Spartan-6 XC6SLX25T-CSG324` FPGA on board. I am using an Altera U…