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I would like to contribute and create a defconfig for the zybo z7-10 board - where to begin?
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I want to run RISC-V rocket-chip on Zynq FPGA Board (Zybo Z7), what are the constraints I have to add to the project?
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Hi @dpaul24,
I've tried to replicate hdmi pass through project from your repo but got some critical warnings I don't know how to solve and don't know why that happened. Could you help to take a look?…
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Hi rkharris, thanks for this project. I have digilent zybo z7-10 board and I synthesis succesfully. But I got error about LUT size. I think my fpga version a little bit lower than you. Do you have an…
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Hi,
I want to get image from Pcam 5C from Ubuntu running on ZYBO-Z7-20.
First, I cloned this repository, and tested pre-built image. I could get camera image by command-line.
Next, To use ubunt…
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### 現象
- zybo-z7-10-pmods-petalinux.bit.bin
- zybo-z7-10-pmods-petalinux.dtbo
を以下の手順で読み込むと Bitstream, dtbo のロードは成功し、 GPIO として使えるようになるが
```
cdns-i2c e0004000.i2c: timeout waiting on completi…
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Dear @btashton,
What are the IP cores should be added in Zybo Z7 platform which is already written in litex-boards( https://github.com/litex-hub/litex-boards)
Does generating the bitstream with…
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I am trying to implement the Canny edge detection in SDx 2017.4 using the release of 2017.4.
I imported the files in the folder Canny to do so, and I tried to solve some problems related to data type…
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Can you consider to implement generic uio in your python periphery? As i see your MMIO implementation can serve the reg mapping for a /dev/uioX, only the IRQ waiting which is needed to implemented for…
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In order to access ZYBO Z7-20 without setting IP address manually, it is better to add a static IP address for eth0 as default in creating root file system.