AugustinJose1221 / FPGA-Build

A novel architectural design for stitching video streams in real-time on an FPGA.
MIT License
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fpga frame-stitching gaussian-kernel image image-processing keypoint real-time stitching-algorithm verilog video-frames

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FPGA Architecture for Real-time Video Stitching

A novel architectural design for stitching video streams in real-time on an FPGA.
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Table of Contents
  1. About The Project
  2. Getting Started
  3. Usage
  4. Roadmap
  5. Contributing
  6. License
  7. Contact

About The Project

The designed architecture generates a video having a wider feild of view by stitching two video input based on features and keypoints. In simple terms, the output generated will be a panorama but with video. The architecture is optimized such that the output can be produced in real-time.

Algorithm

The figure below illustrates the block diagram of the system depicting each step of the algorithm.

Block Diagram

The system can be broadly divided into three subystems:

Preprocessing

The input video stream for the system is in 8 bit RGB format. The input 8 bit image is shown in figure. Each individual frame of the video stream will have three channels corresponding to red, green and blue. The colour information in the video frames does not enhance feature detection. Moreover, computation on a 3 channel 8 bit image takes more time compared to a single channel 8 bit image. Therefore, the RGB video frame is converted to an 8 bit grayscale image. The generated grayscale images will have lesser noise, more details in the shadows and provides better computational efficiency, shown in figure.

Input image Grayscale image
Input image Grayscale image

SIFT Based Feature Extraction

Feature extraction from the grayscale images is done using SIFT algorithm. SIFT algorithm can be separated into two main steps:

Frame Stitching

Frame stitching is the process of combining two frames into a single image. Frame stitching is done in two steps:

Getting Started

Prerequisites

The following packages needs to be installed on the Linux system before executing the source code.

Installation

  1. Clone the repo
    git clone https://github.com/AugustinJose1221/FPGA-Build.git
  2. Change working directory
    cd FPGA-Build/make
  3. Compile the design
    make create
  4. To view the RTL waveform
    make simulate
  5. Generate output image
    python3 hexToImage.py

    Usage

    Project Tree

Roadmap

See the open issues for a list of proposed features (and known issues).

Contributing

Any contributions you make are greatly appreciated.

  1. Fork the Project
  2. Create your Feature Branch (git checkout -b feature/AmazingFeature)
  3. Commit your Changes (git commit -m 'Add some AmazingFeature')
  4. Push to the Branch (git push origin feature/AmazingFeature)
  5. Open a Pull Request

License

Distributed under the MIT License. See LICENSE for more information.

Contact

Twitter: @augustinjose121
Gmail: augustinjose1221@gmail..com
Discuss: Github Discussions