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ERC-IIITH
/
Verilog-Library
Comprehensive hardware library in Verilog for hardware primitives
MIT License
4
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11
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Added basic nbit register
#29
madhavpcm
closed
2 years ago
0
Positive edge triggered D Flip Flop
#28
The-Endurance
closed
2 years ago
0
Added files for an 8 bit ALU with basic functionalities
#27
KarthikL1729
opened
2 years ago
1
Active high 7 Segment Display
#26
The-Endurance
opened
2 years ago
1
SR Flip Flop; positive edge triggered
#25
The-Endurance
closed
2 years ago
0
Added module and testbench for JK flipflop with behavioural implementation
#24
KarthikL1729
closed
2 years ago
0
Added files for two input NAND
#23
The-Endurance
closed
2 years ago
0
Added module and testbench file for decade counter
#22
KarthikL1729
closed
2 years ago
0
Full subtractor
#21
Anonymous-AAA
closed
3 years ago
0
Demux1x2
#20
Anonymous-AAA
closed
3 years ago
0
Committing Half Subtractor
#19
Anonymous-AAA
closed
3 years ago
2
Adder branch
#18
madhavpcm
closed
3 years ago
2
Committed half_adder to the repo
#17
Anonymous-AAA
closed
3 years ago
0
and gate
#16
challatharun
closed
3 years ago
0
added AND gate
#15
challatharun
closed
3 years ago
0
Decade Counter
#14
adithyasunil26
closed
2 years ago
2
Add LICENSE and .gitattributes [fixes #7]
#13
CyberCitizen01
closed
3 years ago
0
Added Up_down counter
#12
swastik1308
closed
3 years ago
0
Added parameterized Up-Down counter
#11
swastik1308
closed
3 years ago
0
Made the required changes as mentioned
#10
Siddharth1002
closed
2 years ago
1
Added BoothMultiplier in verilog
#9
nandita-manchikanti
closed
2 years ago
2
Added files for structural and RTL XOR gate implementation
#8
KarthikL1729
closed
3 years ago
0
Add License and a .gitattributes file
#7
CyberCitizen01
closed
3 years ago
0
D-Flipflop
#6
adithyasunil26
closed
2 years ago
5
Gates
#5
adithyasunil26
opened
3 years ago
6
Added T flip flop
#4
swastik1308
closed
3 years ago
4
4x1 MUX
#3
adithyasunil26
closed
3 years ago
0
2x1 MUX
#2
adithyasunil26
closed
3 years ago
0
Added README and CONTRIBUTING
#1
adithyasunil26
closed
3 years ago
0