Description
In this project I have designed a system that shows the DSP capabilities of FPGA systems. The FPGA design consists of:
1) A finite-state machine for the audio codec configuration via I2C.
2) An I2S receiver for acquiring data from the audio codec.
3) A 6-order low-pass IIR filter to demonstrate filtering capabilities of FPGA.
4) A 4096-point FFT megacore from Altera to get the signal spectrum.
5) A VGA module with video RAM to display the spectrum.
All modules are written by myself except FFT megacore.
The design is intended for the Terasic DE2-115 board with the Cyclone IV FPGA chip.
KEY[0] - reset
SW[2:0] - background color
SW[17] - 1: filter off, 0: filter on
SW[16] - mic left/right channel
VGA: VESA 1024x768@70 Hz
FFT range: 0 - 1/4 Fs
Fs: 48 828.125 Hz
Block diagram
