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Some memories fail to be synthesised to FPGA BRAM, [while running quartus toolchain targeted to DE2-115 (EP4CE115) with LiteX]
Instruction caches sythetises to 74k LUTs taking most of the device :(…
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Can you tell me how to implement your DE2-115 code in Quartus?Or what platform should I build to make use of your Makefile?
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I'm trying to repeat the ISP1362 VHDL interface for DE2-115 board. In the old edition, it has the same ISP1362.
I changed some necessary OTG pins. After downloading the software, I installed the DE2_…
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### Discussed in https://github.com/t-crest/patmos/discussions/94
Originally posted by **LehrChristoph** September 14, 2021
Hi all,
I started to develop a container image which provides all…
Emoun updated
4 months ago
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Hi,
Looks like you have the Ethernet working in u-boot for the DE2-115? Any chance for a upload of the associated hardware design - or at least the .qsys file for the soc?
Thanks for posting th…
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Hi,
I am trying to build rocket chip for terasic de2115. There are some issues which i think some one with more knowledge on rocket support for de2115 could clarify more and suggest fixes.
I fi…
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Hi,
I am trying litex to generate a rocket based soc for terrasic de2 115.
Command i used to build is:
`litex-boards/litex_boards/targets/terasic_de2_115.py --build --cpu-type rocket --cpu-va…
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Currently, the synthesize and program [targets](https://github.com/jbush001/NyuziProcessor/blob/master/hardware/fpga/de2-115/CMakeLists.txt) for the DE2-115 board only support JTAG mode, generating a …
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I'm using Amaranth for university classes, where the students have access to DE1-SoC and DE2-115 boards. The board definition for DE1-SoC in `amaranth-boards` is very incomplete, and there is no defin…
tilk updated
11 months ago
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https://coldnew.github.io/7a67f04e/
手邊有一台早期獲得的 Altera DE2-115 開發平台 ，一直放著積灰塵也不是辦法，再加上最近想多玩玩 FGPA，所以就來重新玩一次吧 :) 和 Xilinx Zybo Board 不同，Altera DE2-115 開發平台 是只有 FPGA 的開發板，並未包含 ARM Cortex-A9 來作為輔助用的 …