kuznia-rdzeni coreblocks issues

kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes

https://kuznia-rdzeni.github.io/coreblocks/

BSD 3-Clause "New" or "Revised" License

38 stars 16 forks source link

issues

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Newest Most commented Recently updated Oldest Least commented Least recently updated

Superscalar instruction decoding

#769 tilk opened 9 hours ago
0
Far path for fpu adder/subtractor

#768 Durchbruchswagen opened 18 hours ago
0
Update documentation after separating Transactron

#767 Hazardu opened 23 hours ago
1
Use bit vector allocator for free registers

#766 tilk opened 6 days ago
3
Synchronous register file using MemoryBank

#765 tilk opened 6 days ago
2
RISC-V Debug Specification

#764 piotro888 opened 1 week ago
0
Instruction tracking debugging interface

#763 piotro888 opened 1 week ago
0
Delay flush by one cycle

#762 tilk opened 1 week ago
2
Check for CRLF line endings in CI formatting runs

#761 piotro888 opened 1 week ago
0
Create pyproject.toml

#760 tilk opened 1 week ago
0
RF using async memory

#759 tilk closed 6 days ago
4
External Transactron

#758 tilk closed 1 week ago
3
Accept custom `CoreConfiguration` in `gen_verilog` script

#757 piotro888 opened 1 week ago
0
LiteX support changes

#756 piotro888 closed 1 week ago
3
mtvec vectored mode

#755 kalinf closed 1 week ago
0
Amaranth 0.5.3

#754 tilk closed 1 week ago
2
Pytest option `--coreblocks-test-count` is not compatible with `-k`

#753 tilk opened 2 weeks ago
0
Tests for ManyToOneConnectTrans and TestBackend don't perform any checks

#752 tilk opened 3 weeks ago
0
Support arbitrary signal length in `count_leading_zeros`

#751 tilk opened 3 weeks ago
3
Fix synthesis of some configurations

#750 piotro888 closed 2 weeks ago
0
Memories doesn't synthetise to BRAM in Quartus toolchain

#749 piotro888 opened 3 weeks ago
6
Update toolchain (including GCC to 14)

#748 tilk opened 4 weeks ago
0
Implement zicond

#747 Hazardu closed 6 days ago
0
Upgrade Pyright to latest (387)

#746 tilk opened 4 weeks ago
0
Implement vectored interrupt mode in `mtvec`

#745 piotro888 closed 1 week ago
0
Implement Physical Memory Protection (PMP)

#744 piotro888 opened 4 weeks ago
0
Implement `misa` CSR

#743 piotro888 closed 3 weeks ago
0
RFC 36 (async/await testing)

#742 tilk closed 2 weeks ago
0
LZA (Leading zeros anticipation)

#741 Durchbruchswagen opened 1 month ago
1
Make RS feed FUs with garbage if flushing

#740 Arusekk opened 1 month ago
5
Changeable underlying memory in MemoryBank

#739 tilk closed 3 weeks ago
0
Update Amaranth to before RFC 36

#738 tilk closed 4 weeks ago
2
Register file using synchronous memory

#737 tilk opened 1 month ago
0
Multiport `MemoryBank`

#736 tilk closed 1 month ago
0
Fix WFI resume on mstatus.MIE disabled

#735 piotro888 closed 1 month ago
1
Implement multi-ported FPGA memories

#734 tilk opened 2 months ago
0
Update Amaranth to after RFC 58

#733 tilk closed 1 month ago
13
Update Amaranth to just before RFC 27

#732 tilk closed 2 months ago
0
Add `def_methods`

#731 tilk closed 2 months ago
0
Clean up `MemoryBank`

#730 tilk closed 2 months ago
0
User Mode and remaining mstatus fields

#729 piotro888 closed 1 month ago
0
FPU rounding module

#728 Durchbruchswagen closed 3 weeks ago
1
Hash functions and CountHashTab

#727 lekcyjna123 opened 3 months ago
1
IOInterface typing wrapper for lib.data signatures

#726 piotro888 opened 3 months ago
1
Support loading initialized data memory from asm tests

#725 piotro888 closed 3 months ago
0
Fix `mepc` alignment

#724 piotro888 closed 3 months ago
0
Support top-level signals in TransactionComponent

#723 piotro888 closed 2 months ago
2
More uses of av_comb, slight refactor of RF

#722 tilk closed 1 month ago
2
Add a trap handler to the benchmark framework

#721 xThaid closed 4 months ago
1
Ftq

#720 xThaid closed 5 months ago
0