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HoneyGol-Microsystems
/
vesp-alpha
RISC-V based student processor for embedded applications.
GNU General Public License v3.0
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create Arduino like GPIO interface
#110
medexs
opened
9 months ago
0
Add read enable (or similar) to address decoder
#109
andreondra
closed
1 month ago
1
Allow to open RTL analysis in Vivado
#108
andreondra
closed
9 months ago
0
Add possibility to start vivado gui after running test
#107
andreondra
closed
9 months ago
0
Add swtest support
#106
andreondra
closed
1 month ago
0
Make split memory default, change only in rv test related recipe
#105
andreondra
opened
9 months ago
0
Clean files created by VS Code's usage of xvlog in make.py clean
#104
andreondra
closed
9 months ago
0
51 update readme with compilation and deploying on fpga
#103
medexs
closed
10 months ago
0
Fix screwed up logo in README on mobile
#102
andreondra
closed
1 month ago
0
Added projects logo
#101
andreondra
closed
10 months ago
0
Added clean fn to make.py
#100
andreondra
closed
10 months ago
0
make.py: creating a Vivado project
#99
andreondra
closed
10 months ago
0
96 exclude unused functions during compilation
#98
medexs
closed
10 months ago
0
94 fix makefile
#97
medexs
closed
10 months ago
0
Find a way to exclude unused functions during compilation
#96
medexs
closed
10 months ago
0
FIx `elftohex.py` error checking
#95
medexs
opened
10 months ago
0
Fix Makefile
#94
medexs
closed
10 months ago
2
85 reorganize directory with sw
#93
medexs
closed
10 months ago
0
Added Vivado as a default simulation runner.
#92
andreondra
closed
10 months ago
0
Add very simple command to generate a project and launch Vivado using make.py
#91
andreondra
closed
10 months ago
0
Catch OSError in recipeProcessor in run step
#90
andreondra
opened
10 months ago
0
Find a way to integrate Vivado linter to VS Code
#89
andreondra
closed
9 months ago
1
Add setup phase to make.py
#88
andreondra
closed
1 month ago
3
Added non-blocking assignments to FIFO
#87
andreondra
closed
10 months ago
0
Consider using already built RISC-V toolchain
#86
medexs
opened
10 months ago
1
Reorganize directory with SW
#85
medexs
closed
10 months ago
0
82 standalone asm compilation
#84
medexs
closed
10 months ago
0
Rewrite Verilog to SystemVerilog
#83
medexs
closed
6 months ago
0
Compile C firmware and standalone programs efficiently
#82
medexs
closed
10 months ago
1
[make.py] halt on error functionality
#81
andreondra
closed
1 month ago
2
change casex to casez
#80
medexs
closed
10 months ago
0
remove r0 register
#79
medexs
closed
10 months ago
0
Remove `r0` register
#78
medexs
closed
10 months ago
0
Rewrite casex to casez
#77
medexs
closed
10 months ago
0
rename some signals
#76
medexs
closed
10 months ago
0
Create automatic Vivado synth+impl builds
#75
andreondra
opened
10 months ago
0
[WIP] Refactored testing in make.py
#74
andreondra
closed
10 months ago
0
Create a portable dev environment
#73
andreondra
closed
9 months ago
0
Hotflix: Removed elftools usage from make.py
#72
andreondra
closed
11 months ago
0
Create GPIO testbench
#71
andreondra
closed
11 months ago
1
CPU and repository name
#70
medexs
closed
10 months ago
9
Create TB for CPU+GPIO+Firmware in C
#69
medexs
closed
9 months ago
2
Fix FIFO
#68
andreondra
closed
10 months ago
0
make.py even more abstraction
#67
andreondra
closed
1 month ago
3
Basic make.py fixes
#66
andreondra
closed
11 months ago
0
make.py philosophy overhaul
#65
andreondra
closed
10 months ago
0
Added FIFO primitive
#64
andreondra
closed
11 months ago
0
make.py ignores errors from iverilog
#63
medexs
closed
10 months ago
0
make.py TypeError exception when no arguments are passed
#62
medexs
closed
11 months ago
5
Startup code
#61
medexs
closed
11 months ago
0
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