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HoneyGol-Microsystems
/
vesp-alpha
RISC-V based student processor for embedded applications.
GNU General Public License v3.0
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Figure out problems with timing analysis
#60
andreondra
closed
11 months ago
1
Added preliminary peripheral support
#59
andreondra
closed
9 months ago
0
Find a place for a documentation
#58
andreondra
closed
1 month ago
4
Create address decoder generator
#57
andreondra
closed
1 month ago
0
fix memory instances, adjust section sizes
#56
medexs
closed
12 months ago
0
separate instr and data memory, instantiate it
#55
medexs
closed
1 year ago
0
Added exception triggers for unknown instructions
#54
andreondra
closed
1 year ago
0
add custom linker script
#53
medexs
closed
1 year ago
0
Rewrite bash scripts to Python
#52
andreondra
closed
1 year ago
0
update README with compilation and deploying on FPGA
#51
andreondra
closed
10 months ago
2
Separate memory (instructions, data)
#50
andreondra
closed
1 year ago
0
Add breakpoint support
#49
andreondra
opened
1 year ago
0
Add illegal instructions "support"
#48
andreondra
closed
1 year ago
0
Add possibility to launch individual tests using make.py
#47
andreondra
closed
10 months ago
0
Add convert function docs
#46
andreondra
closed
10 months ago
1
Add convert function to make.py
#45
andreondra
closed
1 year ago
0
Add clean function to make.py
#44
andreondra
closed
10 months ago
2
Pass ebreak test
#43
andreondra
closed
1 year ago
0
Consider using Jupyter for some examples
#42
andreondra
closed
11 months ago
1
[Example Apps] Add Doom support
#41
andreondra
opened
1 year ago
0
TODO: Added interrupt controller and exceptions support
#40
andreondra
closed
1 year ago
1
Add mtvec support
#39
andreondra
closed
1 year ago
0
Add exception support
#38
andreondra
opened
1 year ago
0
Add mret support
#37
andreondra
closed
1 year ago
0
Added CSR tests
#36
andreondra
closed
1 year ago
0
M extension
#35
medexs
closed
9 months ago
1
Added synchronization to reset input
#34
andreondra
closed
1 year ago
0
add docs for compiling .S files to .hex
#33
medexs
closed
1 year ago
0
All test statistics when running `test` option
#32
medexs
closed
10 months ago
1
Add synchronizer to reset input
#31
andreondra
closed
1 year ago
0
Added first memory map proposal.
#30
andreondra
closed
1 year ago
0
[Tests] Add continuous automatic tests to GitHub
#29
andreondra
opened
1 year ago
3
Added synchronizer with test
#28
andreondra
closed
1 year ago
0
Add variable-stage synchronizer
#27
andreondra
closed
1 year ago
0
Added CSR
#26
andreondra
closed
1 year ago
1
ASM to FPGA support
#25
medexs
closed
1 year ago
0
[Memory] Create memory map
#24
andreondra
closed
11 months ago
0
[Extensions] Add M extension
#23
andreondra
closed
11 months ago
1
[CSR] Add CSR
#22
andreondra
closed
1 year ago
0
[Interrupt controller] Design
#21
andreondra
opened
1 year ago
1
Added tests submodule.
#20
andreondra
closed
1 year ago
0
Add risc-v tests forked source as a submodule
#19
andreondra
closed
1 year ago
0
fix shift amount
#18
medexs
closed
1 year ago
0
Optimize critical path
#17
andreondra
closed
11 months ago
5
Fix multiple include error
#16
andreondra
closed
1 year ago
2
Find and integrate simple assembler to project
#15
andreondra
closed
1 year ago
3
Fix SLL, SRA, SRL instructions
#14
andreondra
closed
1 year ago
1
Add PWM generator
#13
andreondra
opened
1 year ago
1
RISC-V tests top entity
#12
andreondra
closed
1 year ago
0
Create a simple way to load binaries to generated design
#11
andreondra
closed
1 year ago
1
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