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LibreRouterOrg
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LibreRouter hardware repository
https://librerouter.org
GNU Affero General Public License v3.0
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Change JATG pull down resistors Value
#64
xcancerberox
opened
4 years ago
0
Many improvements
#63
spiccinini
opened
4 years ago
5
General Silk screen check
#62
xcancerberox
opened
4 years ago
0
Add a way to disconnect the power to the board through GPIO
#61
spiccinini
opened
4 years ago
3
Properly design coupled transmission lines
#60
spiccinini
opened
4 years ago
2
Missing Core Board?
#59
stephen304
opened
4 years ago
2
Missing holes in PCB
#58
xcancerberox
opened
4 years ago
6
Improve Ethernet differential pair impedance and reduce series resistance
#57
xcancerberox
closed
4 years ago
2
Mega board pcie big move
#56
xcancerberox
closed
4 years ago
0
Remove SPI connection from watchdog to core board (introduced by mistake in the Eagle to Kicad migration)
#55
spiccinini
closed
4 years ago
1
Improve impedance of PCIe routing
#54
spiccinini
closed
4 years ago
4
Mega board bom completion part A
#53
xcancerberox
closed
4 years ago
1
add enclosure drawing
#52
spiccinini
closed
4 years ago
0
Complete BOM
#51
xcancerberox
opened
5 years ago
7
General track and vias review
#50
xcancerberox
opened
5 years ago
0
Add JTAG connector
#49
xcancerberox
opened
5 years ago
1
Shorten GPS uart path
#48
xcancerberox
closed
4 years ago
1
Power domain isolation
#47
xcancerberox
opened
5 years ago
2
Add magnetics board option
#46
xcancerberox
opened
5 years ago
1
Add hack ethernet port
#45
xcancerberox
closed
4 years ago
1
Individual disable for PCIe0 and 1
#44
xcancerberox
closed
4 years ago
1
Change GPS 3.3V source
#43
xcancerberox
closed
4 years ago
1
Change PCIe1 3.3V source
#42
xcancerberox
closed
4 years ago
2
Move PCIe1 device
#41
xcancerberox
closed
4 years ago
1
Mega board v1.3.0
#40
xcancerberox
closed
5 years ago
2
Internal RF cables may disconnect or shortcircuit
#39
spiccinini
closed
4 years ago
1
Change custom variable to default variable
#38
xcancerberox
closed
5 years ago
0
Pin connection difference between PCIe0 and PCIe1
#37
xcancerberox
closed
5 years ago
1
Mega board kicad dev
#36
xcancerberox
closed
5 years ago
5
First aproach to general block diagram
#35
xcancerberox
closed
5 years ago
1
Better PoE power handling in both LAN and WAN ports
#34
spiccinini
closed
4 years ago
4
Add internal header for Core9558 ethernet ports not used
#33
xcancerberox
closed
4 years ago
1
Dividing doc and design folders
#32
xcancerberox
closed
5 years ago
0
GPS module does not lock (signal issues)
#31
spiccinini
opened
5 years ago
5
add specs to the Readme
#30
spiccinini
closed
5 years ago
1
PCB's process parameter
#29
chenhaimeng
opened
5 years ago
1
PoE passthrough circuit R32 is too low
#28
spiccinini
closed
5 years ago
2
Dragino PoE injector does not support 1000mbps
#27
spiccinini
opened
5 years ago
0
Improve 5.8GHz antenna's pigtails
#26
spiccinini
closed
5 years ago
1
Input voltage is <= 30V
#25
spiccinini
closed
5 years ago
8
Added phase2 schematic, gerber and photos
#24
spiccinini
closed
5 years ago
0
PoE and PoE Passthrough overheats magnetics
#23
spiccinini
closed
5 years ago
7
Board hangs when power cycled with serial TTL connected
#22
darkdrgn2k
closed
5 years ago
5
2.4 Ghz radio issue
#21
nicopace
closed
6 years ago
12
Prototypes have fake and reused MAC addresses
#20
altergui
closed
5 years ago
3
we don't have a bootloader
#19
dangowrt
closed
5 years ago
1
PCIe mounting holes are misaligned
#18
nicopace
closed
5 years ago
3
Screen print font
#17
nicopace
closed
5 years ago
3
LEDs for 5GHz WLAN Operation
#16
nicopace
closed
5 years ago
3
Ethernet connector wiring
#15
nicopace
closed
6 years ago
1
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