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NYU-Processor-Design
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nyu-core
The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.
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Module: L3 Data Cache
#24
ShinyMiraidon
opened
1 year ago
2
Module: L1 Instruction Cache
#23
ShinyMiraidon
opened
1 year ago
0
Ignore
#22
ShinyMiraidon
closed
1 year ago
0
Ignore
#21
ShinyMiraidon
closed
1 year ago
0
Module: Program Counter
#20
ShinyMiraidon
opened
1 year ago
1
Ignore
#19
ShinyMiraidon
closed
1 year ago
0
Module: L2 Data Cache
#18
ShinyMiraidon
opened
1 year ago
1
Module: L1 Data Cache
#17
ShinyMiraidon
opened
1 year ago
4
Module: Data Cache Manager
#16
ShinyMiraidon
opened
1 year ago
2
Module: Immediate Sign Extension
#15
ShinyMiraidon
closed
1 year ago
1
Module: ALU
#14
ShinyMiraidon
opened
1 year ago
1
Module: Pipeline Reset Module
#13
ShinyMiraidon
opened
1 year ago
0
Module: Hazard Detection
#12
ShinyMiraidon
closed
12 months ago
0
Module: Branch Evaluator
#11
ShinyMiraidon
opened
1 year ago
1
Module: General Control Module
#10
ShinyMiraidon
opened
1 year ago
0
Module: MEM/WB Latch
#9
ShinyMiraidon
opened
1 year ago
1
Module: EX/MEM Latch
#8
ShinyMiraidon
opened
1 year ago
0
Module: ID/EX Latch
#7
ShinyMiraidon
opened
1 year ago
0
Module: IF/ID Latch
#6
ShinyMiraidon
opened
1 year ago
1
Module: CPU General Purpose Registers
#5
ShinyMiraidon
opened
1 year ago
1
Parameterized ALU and Sign Extension
#4
ShinyMiraidon
closed
1 year ago
1
Update ALU and Sign Extension
#3
ShinyMiraidon
closed
1 year ago
0
Added Sign Extension Module
#2
ShinyMiraidon
closed
1 year ago
3
added ALU module and test
#1
ShinyMiraidon
closed
1 year ago
3
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